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EAi is a member of the Altera Consultants Alliance Program, a network of consulting service providers. EAi provides design assistance nationwide, often to customers new to Altera components and software. Below are some of the suggestions generated by the most frequent questions.

  • Reserve ( assign ) signal names to all of the dedicated inputs to prevent the compiler from using these pins as logic inputs. In SRAM parts GLOBAL signals can be driven from an inside signal. The corresponding external pin must be grounded. It is wise to ground the unused dedicated pins prior to artwork. In EEPROM based parts this internal connection is not available. Internally generated signals for GLOBAL use should exit the device near the dedicated pin that it will connect to. Dedicated pins for most parts can have multiple uses ( clock, clear, etc. ). Check the family data sheet to verify availability for the intended use.

  • Allow the compiler to select the pin assignments (except dedicated inputs). Don't lock the pins till necessary for artwork.

  • Use EEPROM based devices for implementing combinatorial logic. Combinatorial logic in SRAM parts has decoding spikes (glitches) due to the multiplexer architecture of the device. Think synchronous when implementing logic in SRAM parts.

  • Never use a global signal as a logic term. Doing so may prevent global use. The warning message you receive sounds harmless. The results are not.

  • Never use combinatorial logic for clocks, clears or presets in SRAM parts. Remember, look-up tables cannot provide glitchless AND or OR functions.

  • If there are spare outputs, connect several to a header for connecting a logic analyzer. These pins can be named TEST[X..0]. Inside the device connect any signal you wish to one of these test signals. It's almost as good as probing the device. It can also be helpful in simulations when the compiler minimizes out some of your signals. Tie the signal to a test pin and it won't get factored out. This may change the timing slightly.

  • The compiler gives warning messages for unused signals in a design. Sometimes these are unused counter output bits, bits in an array, etc. Signals like these that will never be used can be tied into a giant AND gate. Connect the AND output to an unused output pin to prevent the compiler from minimizing it out. Now all those excess warnings go away and you can spend your time looking at the legitimate ones.

  • Design logic for testability. Many designers use 20% of the device to build in test equipment and/or function generators. If there isn't enough room inside the device for the test logic, use the next larger device for simulation testing.

  • The quest for speed.
    Use good architecture to increase speed rather than running the clock as fast as possible. Use pipelining, parallel operation and efficient controllers to increase system speed. There are simple speedups like setting the compiler to "FAST" mode and enabling cascades and carries for as long a path as you require. Use Clique and hand placement of gates only if absolutely necessary.

    Use the library LPMs for functions such as multiply, adders and counters. Many arithmetic designs use multiply/accumulate algorithms. Multipliers are easily pipelined to increase speed but accumulators pose a more difficult control problem when pipelined. The accumulator usually runs slower than the pipelined multiply. If the compiler settings cannot produce a fast enough adder, we have some adder techniques that will increase the speed by 2-4 times depending upon the number of bits. Since multiply hardware is just a lot of adders, this same architecture can be used to increase multiply pipeline speed. If more multiply speed is required, there are some "number base conversion" schemes to further increase speed and reduce hardware.

    Counters use the same carry logic as adders and the same compiler settings used for adders can help here. For long counters, similar techniques to the fast adder can be employed to increase speed.

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